Nanoscale Field Effect Transistors: Emerging Applications

We are constantly looking to scale down the dimensions of transistors to increase density in the same specific area and at the same time, having powerful functions and increased performance. We have now reached the stage of submicron technology where MOSFETs (metal oxide semiconductor field effect transistors) and FinFETs (fin shaped field effect transistors) cannot be scaled down further. MOSFETs replaced BJTs decades ago, but now transistors seem to have hit their end. While semiconductor giants have a road map to produce 2 nm transistors, scaling down further is next to impossible. Later, FinFETs were considered as their 3-dimensional structure enabled greater density, greater computational power, and lower switching times. But scaling down also means more thermal generation. Thermal effects, high capacitances, and high fabrication costs deemed FinFETs not very suitable for scaling down beyond 7nm. How can we enable transistors to scale down further and follow Moore’s law? The next apparent step would be nanotechnology. While it could be a revolution in VLSI it comes with its own cons and challenges. While there is a lot of research going on regarding the same, this chapter will discuss types of nanomaterials based on dimensions like 0D, 1D, 2D, and 3D, and their respective roles in semiconductor FETs and why it is the next sensible step in the semiconductor industry. 

Low-power application devices and inexpensive transistors are essential for today's technological world. A 3 nm MOSFET nanoelectronic device has just been created by researchers. Even though a MOSFET shrinks in size and uses less power, SCEs still cause a few problems, leakage current, including Hot electron, Impact Ionization, threshold voltage roll-off, Drain Induced Barrier Lowering (DIBL), and others. One of the best-proposed structures to replace the MOSFET structure is the FIN FET structure, which overcomes the limitations brought on by the CMOS transistor. For low-power applications, the FIN FET structure is ideal. A FINFET structure achieves an average subthreshold swing of 60 mv/decade at room temperature beyond the boundaries of CMOS. This paper examines the performance of the many FINFET architectures that have been proposed, including the double gate, tri-gate, and Gate All Around FET. 

Researchers are motivated to develop novel electronic switches with improved low power properties and reduced short channel effects due to the downscaling of conventional MOSFETs (SCE). Using multi-gate FinFET technology could improve control of the gate over the channel charge. We have discussed FinFETs, or multigate transistors, in this chapter. The chapter will include the classification and detailed physics inside the device. The Fabrication section will explain the steps involved in manufacturing the device. The difficulties with FinFET technologies have also been discussed in order to examine the research gap. The performance improvement engineering techniques will give exposure to further improvement techniques in the device. The circuit applications will address the various analog/digital circuits based on FinFET. 

A number of ultra-low power applications that don't need high performance can gain power from running at the lowest supply voltage possible. Scaling the supply voltage is a useful technique for cutting the energy needed by digital circuitry. Based on Shannon's channel capacity theorem, the fundamental limit for supply voltage for planar CMOS circuits has been determined to be 36 mV. FinFET devices fit ultra-low voltage applications better than planar devices because of their nearly excellent sub-threshold properties. For the first time, the fundamental supply voltage limit for logic circuits using FinFETs has been defined in this work. It is discovered that this theoretical limit is considerably lower than the limit for planar CMOS devices. On this fundamental limit, the impact of temperature variations and device design characteristics is also investigated. Other logic gates, such as the NAND gate, are included in the analysis. To determine this fundamental limit for a FinFET device, a novel physics-based, semi-empirical current equation valid for supply voltage below 100 mV has been proposed. This is because the operation of a FinFET device in the ultra-low voltage domain differs significantly from that of its planar counterpart. A circuit designer values a current model like this because it makes calculations for back of the envelope calculations simple. The proposed model is then used to study the logic gates functioning in this regime.

A graphene based FET can be used for a variety of applications. It can be utilized in the fascinating field of nano-scale device electronics or microwave and terahertz based guided wave components. In this chapter, a review of graphene field effect transistors has been presented in RF and bio-sensor circuits. It begins with an overview of the superior properties of graphene in graphene FETs, moving further to the characterization and fabrication challenges, and thereafter, their application in bioanalytical sensing and high frequency devices has been investigated. Graphene material has potential advantages in the form of low losses and power dissipation due to its high thermal, electrical conductivities and mobilities. It leads to better performance and efficiency relative to its silicon counterparts in various applications. It has some design and fabrication challenges owing to its high surface density and single atomic thickness. It also shows limitations in terms of bandgap variation, high fabrication costs and current saturation features.

In this chapter, we explained a detailed physical insight of Negative Differential Resistance (NDR) to Positive Differential Resistance (PDR) transition in a ferroelectric-based negative capacitance (NC) FET and its dependence on the device terminal voltages. Using extensive well-calibrated TCAD simulations, we have investigated this phenomenon on FDSOI NCFET. The NDR to PDR transition occurs due to the Ferroelectric (FE) layer capacitance changes from a negative to a positive state during channel pinch-off. This, in turn, results in a valley point in the output characteristic (IDS-VDS) at which the output resistance is infinite. We also found that we could alter the valley point location by modulating the vertical Electric field through the FE layer in the channel pinch-off region using body bias (VBB). The interface oxide charges also impacted the NDR to PDR transition, and a positive interface charge resulted in a faster NDR to PDR transition. Further, we have utilized the modulation in NDR to PDR transition due to VBack for designing a current mirror. Results show that the output current (IOUT) variation due to VDS, reduces from ~8% to ~2% with VBack. We have also designed a single-stage common source (CS) amplifier and provided design guidelines to achieve a higher gain in the NDR region. The results obtained using a small-signal model of the FDSOI-NCFET demonstrate that ~25% higher gain can be achieved with the discussed design guidelines in the NDR region compared to the transition region of IDS-VDS. We have also explored the device scaling effect on the amplifier gain and found that ~2.23x gain can be increased with a smaller channel length and higher device width.

The continuous development of CMOS technology today beyond many obstacles has been witnessed by all of us. After three decades of aggressive scaling to ever-smaller dimensions, today, MOSFET gate lengths can be less than 22 nm. There are many challenges and limitations at the device level. Short channel effects, such as drain induced barrier lowering, Vth roll-off, gate induced drain leakage, static leakage, punch through, and contact resistance, are among the major blockades for sub-22 nm technology. Many physicists have explored this extremely small dimension device and the effects of charge and energy quantization, and that emerged the concept of single electron conduction. Single-electron devices were being seen as one of the finest beyond-CMOS nanodevices reported by many researchers and ITRS. These devices were facing many roadblocks due to their ultra-small dimensions, fabrication viabilities, room temperature operation, CMOS compatible processes, and lack of simulation methodology. Since the last decade, the evolution of advanced e-beam lithography, Chemical-Mechanical polishing and deposition techniques has gained many researchers’ attention, and the trend to explore these devices is going continuously in an upward direction. Though it is difficult to replace CMOS technology completely, the hybridization of these devices with CMOS is one of the major interests shown by many research works.

Designing electronic devices with higher efficiency while using reduced power is a problem in the field of electronics. Digital technology utilization is increasing due to its higher speeds, lower power requirements, and stability. Accessing data requires a lot of time, so a circuit is created that will be close to the CPU to provide the information that is required. Cache memory is a type of SRAM-based faster storing device. To enhance the performance of the SRAM cell, Read Delay (RD), Write Delay (WD), read stability, write stability and power dissipation of the intended circuit should all be carefully considered while designing an efficient SRAM cell. Delay, power dissipation, and circuit stability all trade-off with one other. In this chapter, we will look at delays, average power dissipation (APD), and stability using a variety of cell ratios, pull-up ratios, and supply voltages, and compare how each of these metrics has improved. As miniaturization of post CMOS technology, technology nodes are getting smaller. Because of this, researchers have examined different typologies, ranging from 6T SRAM to 12T SRAM (even-number transistor cell) analysis. Better delays and an improved static noise margin are obtained by increasing the number of transistors per cell, although power dissipation increases as a result. This chapter covers the overall analysis for SRAM cells with 6T, 8T, 10T, and 12T transistors that vary in CR and PR as well as voltage. The circuits are created for the overall study using a 180nm technology file in the Cadence Virtuoso tool.

In today's high-performance chips, comparative analysis and ideas for reducing power consumption have become the dominant factor in overall power consumption. This should reduce the power consumption of high-density chips, which is so great that many new techniques have been developed in the proposal to design low-power circuits and systems. Ultra-thin gate oxides, very low threshold voltages, and short channels are hallmarks of nanoscale chips. Therefore, the most difficult problem that arises in VLSI circuits and systems is power dissipation. This paper provides an overview of sources of leakage currents in sub-micrometer CMOS gates and techniques, limitations, analysis and ideas to reduce leakage currents [1]; an overview of current circuit-level leakage currents [2] for various techniques; also discusses an example of a 1-bit adiabatic ECRL adder which compares the power and delay. This is one way of leakage minimization technique which is caused by switching action. This simulation work is done in cadence tool using FINFET technology which is a very fast-growing technology as compared to CMOS technology [3].