Transition from Conventional FETs to Novel FETs, SOI, Double Gate, Triple Gate, and GAA FETS

Low-power application devices and inexpensive transistors are essential for today's technological world. A 3 nm MOSFET nanoelectronic device has just been created by researchers. Even though a MOSFET shrinks in size and uses less power, SCEs still cause a few problems, leakage current, including Hot electron, Impact Ionization, threshold voltage roll-off, Drain Induced Barrier Lowering (DIBL), and others. One of the best-proposed structures to replace the MOSFET structure is the FIN FET structure, which overcomes the limitations brought on by the CMOS transistor. For low-power applications, the FIN FET structure is ideal. A FINFET structure achieves an average subthreshold swing of 60 mv/decade at room temperature beyond the boundaries of CMOS. This paper examines the performance of the many FINFET architectures that have been proposed, including the double gate, tri-gate, and Gate All Around FET.