Abstract

Electrical behavior of 3D interconnections (redistribution metal lines, through silicon via.,) used in 3D IC stack technologies is explored in this chapter. To well understand the interconnection incidence on 3D system performances, it is important to consider the whole electrical context of the 3D application, including the silicon substrate. As an emerging technology, electrical compact models are needed, notably for 3D interconnects which include Through-Silicon Via, to evaluate with precision 3D systems performances. However, 3D interconnects introduce several challenges in modeling. As a matter of fact, they imply considering the whole electrical context by taking into account for example current paths, couplings between interconnections, couplings with the substrate. Example of simple closed-form expressions describing electrical model of 3D ICs propagation lines is reported. We investigate models of high aspect ratio TSV, on both analytical and numerical methods electromagnetic simulations and RF measurements. This model enables to extract substrate and TSV impedance and parasitic elements. Its full compatibility with SPICE-like solvers should allow an in depth investigation of TSV impact on circuit performance.

Considering the modeling: from any point source, we calculate the impedance spreading out. For this, our approach is, at least, twofold: compact Green function or Transmission Line Model, over or into a multi-layered substrate, is derived by solving Poisson's equation analytically. Rapid evaluation uses the Discrete Cosine Transform and its variations. Using this technique, the substrate coupling and loss in IC's can be analyzed. The algorithms permit to extract impedances between any numbers of embedded contacts. Comparisons are performed, using finite element methods and experiments.