Abstract
Background: The advent of High Performance Computing (HPC) applications and big data
applications has made it imparitive to develop hardware that can match the computing demands. In
such high performance systems, the high speed multipliers are the most sought after components. A
compressor is an important part of the multiplier; it plays a vital role in the performance of multiplier,
also it contributes to the efficiency enhancement of an arithmetic circuit. The 5:2 compressor circuit
design proposed here improves overall performance and efficiency of the arithmetic circuits in
terms of power consumption, delay and power delay product. The proposed 5:2 compressor circuit
was implemented using both CMOS and Carbon Nano Tube Field Effect Transistor (CNTFET) technologies
and it was observed that the proposed circuit has yielded better results with CNTFETs as
compared to MOSFETs.
Methods/Results: The proposed 5:2 compressor circuit was designed with CMOS technology
simulated at 45 nm with voltage supply 1.0 V and compared it with the existing 5:2 compressor
designes to validate the improvements. Thereafter, the proposed design was implemented with CNTFET
technology at 32 nm and simulated with voltage supply 0.6 V. The comparision results of proposed
5:2 compressor with existing designs implemented using CMOS. The results also compare the
proposed design on CMOS and CNTFET technologies for parameters like power, delay, power delay
product.
Conclusion: It can be concluded that the proposed 5:2 compressor gives better results as compared
to the existing 5:2 compressor designs implemeted using CMOS. The improvement in power, delay
and power delay product is approx 30%, 15% and 40% respectively. The proposed circuit of 5:2
compressor is also implemented using CNTFET technology and compared, which further enhances
the results by 30% (power consumption and PDP). Hence, the proposed circuit implemented using
CNTFET gives substantial improvements over the existing circuits.
Keywords:
Carbon nano tubes, carbon nanotube field effect transistor, CNTFET, CNTs, multi walled nanotube, MWNT,
single walled nanotube, SWNT.
Graphical Abstract
[1]
Sahoo SK, Akhilesh G, Sahoo R. Design of a high performance carry generation circuit for ternary full adder using CNTFET. IEEE Int Symposium on Nanoelectronic and Info Systems (iNIS), Bhopal, 2017: pp. 46-9. DOI: 10.1109/iNIS.2017.19
[2]
Lin S, Kim YB, Lombardi F. Design of a CNTFET-based SRAM cell by dual-chirality selection. IEEE Trans Nanotechnol 2010; 9(1): 30-7. DOI: 10.1109/TNANO. 2009.2025128
[5]
Bardhan S, Rahaman H. Analysis of design-oriented compact model for zigzag semiconducting CNTFETs. Int Conf on Electr, Commun Instrument Kolkata, 2014; pp. 1-4. DOI:10. 1109/ICECI.2014. 6767384
[7]
Menon R, Radhakrishnan D. High performance 5:2 compressor architecture. IEEE Proc Circ Dev Syst 2006; 153(5): 447-52. DOI: 10.1049/ip-cds: 20050152
[8]
Sreehari V, Krishna MK, Avinash L, Reddy PS, Srinivas MB. Novel architectures for high-speed and low-power 3-2, 4-2 and 5-2 compressors. In 20th Int Conf on VLSI design; Bangalore, India, 2007: pp. 324-9, DOI: 10.1109/ VLSID.2007.116.
[9]
Tohidi M, Mousazadeh M, Akbari S, Hadidi K, Khoei A. CMOS implementation of a new high speed, glitch-free 5-2 compressor for fast arithmetic operations. In Proc 20th Int Conf Mixed Design Integrat Circuits Syst - MIXDES Gdynia, 2013: pp. 204-8.
[10]
Najafi A, Timarchi S, Najafi A. High-speed energy-efficient 5:2 compressor. 37th Int Convent Info Commun Tech, Electr Microelectr Opatija, Croatia, 2014; pp. 80-4. DOI: 10.1109/MIPRO. 2014.6859537.
[13]
Nishad AK, Chandel R. Analysis of low power high performance XOR gate using GDI technique Int Conf Computat Intell Commun Netwo; Gwalior, 2011; pp. 187-91. DOI: 10.1109/CICN. 2011.37
[15]
Navi K, Rashtian M, Khatir A, Keshavarzian P, Hashemipour O. High speed capacitor-inverter based carbon nanotube full adder Nanoscale Res Lett 2010; 5(5): 859-62. DOI: 10. 1007/s11671- 010-9575-4.
[16]
Lakshmi PV, Sarada M, Srinivasulu A, Pal D. Three novel singlestage full swing 3-input XOR. Int J Electr 2018; 105(8): 1416-32. https://doi.org/10.1080/00207217. 2018. 1460767.
[17]
Sarada M, Srinivasulu A, Pal D. Novel low-supply, differential XOR/ XNOR with rail-to-rail swing, for hamming-code generation. Int J Electr Lett 2018; 6(3): 272-87.