Implementation of a Robust Framework for Low Power Approximate Multiplier Using Novel 3:2 and 4:2 Compressor for Image Processing Applications

Page: [223 - 239] Pages: 17

  • * (Excluding Mailing and Handling)

Abstract

Background: The technique of approximation allows for a trade-off between accuracy, speed, area use, and power usage. It is essential in applications that can withstand errors because even a modest accuracy loss can have a significant impact on the result.

Methods: In this research, a novel approximate adder and exact 3:2 and 4:2 compressors are used to create a power-efficient approximation multiplier. In order to reduce the partial product while keeping a fair level of accuracy, approximate compressors are used.

Results: The proposed approximate multiplier performs better in terms of LUTs, area, memory usage, and power consumption when compared to state-of-the-art work.

Conclusion: The proposed approximate multiplier is applied to two sets of images for image blending to validate the results. PSNR values of 25.49 dB and 24.7 dB were attained for set 1 and set 2, respectively.

Graphical Abstract

[1]
Han, J.; Orshansky, M. Approximate computing: An emerging paradigm for energy-efficient design. ETS’13, Avignon. FranceMay 27-31,; , 2013, pp. 1-6.
[http://dx.doi.org/10.1109/ETS.2013.6569370]
[2]
Venkatesan, R.; Agarwal, A.; Roy, K.; Raghunathan, A. MACACO: Modeling and analysis of circuits for approximate computing; ICCAD, 2011, pp. 667-673.
[3]
Jinghang , Liang. Jie Han; Lombardi, F. New metrics for the reliability of approximate and probabilistic adders. IEEE Trans. Comput., 2013, 62(9), 1760-1771.
[http://dx.doi.org/10.1109/TC.2012.146]
[4]
Kyaw, K.Y.; Goh, W.L.; Yeo, K.S. Low-power high-speed multiplier for error-tolerant application. In: IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC); Hong Kong, China, 2010; pp. 1-4.
[http://dx.doi.org/10.1109/EDSSC.2010.5713751]
[5]
Kulkarni, P.; Gupta, P.; Ercegovac, M. Trading accuracy for power with an Underdesigned Multiplier architecture. In. 24th International Conference on VLSI Design, Chennai, India, , 2011, 346-3512.
[http://dx.doi.org/10.1109/VLSID.2011.51]
[6]
Mahdiani, H.R.; Ahmadi, A.; Fakhraie, S.M.; Lucas, C. Bio-Inspired imprecise computational blocks for efficient VLSI implementation of soft-computing applications. IEEE Trans. Circ. Syst., 2010, 57(4), 14-19.
[7]
Lin, C-H.; Lin, I-C. High accuracy approximate multiplier with error correction. In. IEEE 31st International Conference on Computer Design (ICCD), Asheville, NC, USA, ; , 2013, pp. 33-38.
[http://dx.doi.org/10.1109/ICCD.2013.6657022]
[8]
Bhardwaj, K.; Mane, P.S.; Henkel, J. Power- and area-efficient Approximate Wallace Tree Multiplier for error-resilient systems. In: 15th International Symposium on Quality Electronic Design (ISQED); Santa Clara, CA, USA, 2014; pp. 263-269.
[http://dx.doi.org/ 10.1109/ISQED.2014.6783335.]
[9]
Liu, C.; Han, J.; Lombardi, F. A low-power, high-performance approximate multiplier with configurable partial error recovery DATE 2014; Dresten: Germany, 2014.
[10]
Momeni, A.; Han, J.; Montuschi, P.; Lombardi, F. Design and analysis of approximate compressors for multiplication. IEEE Trans. Comput., 2015, 64(4), 984-994.
[http://dx.doi.org/10.1109/TC.2014.2308214]
[11]
Narayanamoorthy, S.; Moghaddam, H.A.; Liu, Z.; Park, T.; Kim, N.S. Energy-efficient approximate multiplication for digital signal processing and classification applications. IEEE Transactions on Very Large Scale Integration (VLSI). Systems, 2015, 23(6), 1180-1184.
[12]
Van Toan, N.; Lee, J.G. FPGA-based multi-level approximate multipliers for high-performance error-resilient applications. IEEE Access, 2020, 8, 25481-25497.
[http://dx.doi.org/10.1109/ACCESS.2020.2970968]
[13]
Strollo, A.G.M.; Napoli, E.; De Caro, D.; Petra, N.; Meo, G.D. Comparison and extension of approximate 4-2 compressors for low-power approximate multipliers. IEEE Trans. Circuits Syst. I Regul. Pap., 2020, 67(9), 3021-3034.
[http://dx.doi.org/10.1109/TCSI.2020.2988353]
[14]
Yang, Z.; Han, J.; Lombardi, F. Approximate compressors for error-resilient multiplier design. In: IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS); Amherst, MA, USA, 2015; pp. 183-186.
[http://dx.doi.org/ 10.1109/DFT.2015.7315159]
[15]
Venkatachalam, S.; Ko, S. Design of power and area efficient approximate multipliers. IEEE Transactions on Very Large Scale Integration (VLSI). Systems, 2017, 25(5), 1782-1786.
[16]
Ha, M.; Lee, S. Multipliers with approximate 4–2 compressors and error recovery modules. IEEE Embed. Syst. Lett., 2018, 10(1), 6-9.
[http://dx.doi.org/10.1109/LES.2017.2746084]
[17]
Akbari, O.; Kamal, M.; Afzali-Kusha, A.; Pedram, M. Dual-quality 4:2 compressors for utilizing in dynamic accuracy configurable multipliers. IEEE Transactions on Very Large Scale Integration (VLSI). Systems, 2017, 25(4), 1352-1361.
[18]
Sabetzadeh, F.; Moaiyeri, M.H.; Ahmadinejad, M. A majority-based imprecise multiplier for ultra-efficient approximate image multiplication. IEEE Trans. Circuits Syst. I Regul. Pap., 2019, 66(11), 4200-4208.
[http://dx.doi.org/10.1109/TCSI.2019.2918241]
[19]
Ahmadinejad, M.; Moaiyeri, M.H.; Sabetzadeh, F. Energy and area efficient imprecise compressors for approximate multiplication at na-noscale. AEU Int. J. Electron. Commun., 2019, 110, 152859.
[http://dx.doi.org/10.1016/j.aeue.2019.152859]
[20]
Thakur, G.; Sohal, H.; Jain, S. Design and comparative performance analysis of various multiplier circuit. J. Scientific Eng. Res., 2018, 5(7), 340-349.
[21]
Thakur, G.; Sohal, H.; Jain, S. An efficient design of 8-bit high speed parallel prefix adder. Res. J. Sci. Technol., 2018, 10(2), 105-114.
[22]
Jeon, D.; Seok, M.; Zhang, Z.; Blaauw, D.; Sylvester, D. Design methodology for voltage-overscaled ultra-low-power systems. IEEE Trans. Circuits Syst. II Express Briefs, 2012, 59(12), 952-956.
[http://dx.doi.org/10.1109/TCSII.2012.2231036]
[23]
Edavoor, P.J.; Raveendran, S.; Rahulkar, A.D. Approximate multiplier design using novel dual-stage 4:2 compressors. IEEE Access, 2020, 8, 48337-48351.
[http://dx.doi.org/10.1109/ACCESS.2020.2978773]
[24]
Ansari, M.S.; Jiang, H.; Cockburn, B.F.; Han, J. Low-power approximate multipliers using encoded partial products and approximate compressors. IEEE J. Emerg. Sel. Top. Circuits Syst., 2018, 8(3), 404-416.
[http://dx.doi.org/10.1109/JETCAS.2018.2832204]
[25]
Zervakis, G.; Tsoumanis, K.; Xydis, S.; Soudris, D.; Pekmestzi, K. Design-efficient approximate multiplication circuits through partial product perforation. IEEE Transact.Very Large Scale Integr. (VLSI). Syst., 2016, 24(10), 3105-3117.
[26]
Qiqieh, I.; Shafik, R.; Tarawneh, G.; Sokolov, D.; Das, S.; Yakovlev, A. Significance-driven logic compression for energy-efficient multi-plier design. IEEE J. Emerg. Sel. Top. Circuits Syst., 2018, 8(3), 417-430.
[http://dx.doi.org/10.1109/JETCAS.2018.2846410]
[27]
Thakur, G.; Sohal, H.; Jain, S. Design and analysis of high-speed parallel prefix adder for digital circuit design applications. In: International Conference on Computational Performance Evaluation (ComPE); Shillong, India, 2020; pp. 095-100.
[http://dx.doi.org/10.1109/ComPE49325.2020.9200064]
[28]
Toan, N.V.; Lee, J. Energy-area-efficient approximate multipliers for error-tolerant applications on FPGAs. In: 32nd IEEE International System-on-Chip Conference (SOCC); Singapore, 2019; pp. 336-341.
[http://dx.doi.org/10.1109/SOCC46988.2019.1570548202]
[29]
Liu, W.; Qian, L.; Wang, C.; Jiang, H.; Han, J.; Lombardi, F. Design of approximate Radix-4 booth multipliers for error-tolerant computing. IEEE Trans. Comput., 2017, 66(8), 1435-1441.
[http://dx.doi.org/10.1109/TC.2017.2672976]
[30]
Liu, W.; Cao, T.; Yin, P.; Zhu, Y.; Wang, C.; Swartzlander, E.E.; Lombardi, F. Design and analysis of approximate redundant binary multipliers. IEEE Trans. Comput., 2019, 68(6), 804-819.
[http://dx.doi.org/10.1109/TC.2018.2890222]
[31]
Thakur, G.; Sohal, H.; Jain, S. High speed RADIX-2 butterfly structure using novel Wallace multiplier. . Int. J. Eng. Technol.,, 2018, 7(3.4), 213-217.
[http://dx.doi.org/ 10.14419/ijet.v7i3.4.16777]
[32]
Kim, D.; Kung, J.; Mukhopadhyay, S. A power-aware digital multilayer perceptron accelerator with on-chip training based on approximate computing. IEEETransact. Emerg. Topics. Comput., 2017, 5(2), 164-178.
[http://dx.doi.org/10.1109/TETC.2017.2673548]
[33]
Pal, B.; Jain, S. Novel discrete component wavelet transform for detection of cerebrovascular diseases. Sadhana, 2022, 47(4), 237.
[http://dx.doi.org/10.1007/s12046-022-02016-9]
[34]
Salau, A.O.; Jain, S.; Eneh, J.N. A review of various image fusion types and transforms. Indones. J. Electr. Eng. Comput. Sci., 2021, 24(3), 1515-1522.
[http://dx.doi.org/10.11591/ijeecs.v24.i3.pp1515-1522]
[35]
Thakur, G.; Sohal, H.; Jain, S. A novel parallel prefix adder for optimized Radix-2 FFT processor. Multidimens. Syst. Signal Process., 2021, 32(3), 1041-1063.
[http://dx.doi.org/10.1007/s11045-021-00772-1]
[36]
Thakur, G.; Sohal, H.; Jain, S. A novel asic-based variable latency speculative parallel prefix adder for image processing application. Circuits Syst. Signal Process., 2021, 40(11), 5682-5704.
[http://dx.doi.org/10.1007/s00034-021-01741-6]
[37]
Thakur, G.; Sohal, H.; Jain, S. FPGA-based parallel prefix speculative adder for fast computation application. In: Sixth International Conference on Parallel, Distributed and Grid Computing; PDGC: Waknaghat, India, 2020; pp. 206-210.
[http://dx.doi.org/10.1109/PDGC50313.2020.9315783]