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Recent Patents on Nanotechnology

Author(s): Naveenbalaji Gowthaman* and Viranjay M. Srivastava

DOI: 10.2174/1872210517666230427163447

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Investigations on Cylindrical Surrounding Double-gate (CSDG) Mosfet using ALXGA1-XAS/INP: PT with LA2O3 Oxide Layer for Fabrication

Page: [374 - 385] Pages: 12

  • * (Excluding Mailing and Handling)

Abstract

Background/Introduction: The Cylindrical Surrounding Double-Gate MOSFET has been designed using Aluminium Gallium Arsenide in its arbitrary alloy form alongside Indium Phosphide with Lanthanum Dioxide as a high-ƙ dielectric material.

Objective: To conduct research on the novel application of AlxGa1-xAs/InP: Pt with La2O3 oxide layer in the fabrication of Cylindrical Surrounding Double-gate (CSDG) MOSFET, with the ultimate goal of obtaining patentable findings and developing intellectual property in the field. The heterostructure based on the AlxGa1-xAs/InP: Pt has been used in the design and implementation of the MOSFET for RF applications. Platinum serves as the gate material, which has higher electronic immunity toward the Short Channel Effect and highlights semiconductor properties. The charge buildup is the main concern in the field of MOSFET design when two different materials are considered for fabrication.

Methods: The usage of 2 Dimensional Electron Gas has been outstanding in recent years to help the electron buildup and charge carrier accumulation in the MOSFETs regime. Device simulation used for the smart integral systems is an electronic simulator that uses the physical robustness and the mathematical modeling of semiconductor heterostructures. In this research work, the fabrication method of Cylindrical Surrounding Double Gate MOSFET has been discussed and realized. The scaling down of the devices is essential to reduce the area of the chip and heat generation. By using these cylindrical structures, the area of contact with the circuit platform is reduced since the cylinder can be laid down horizontally.

Results: The coulomb scattering rate is observed to be 18.3 % lower than the drain terminal when compared to the source terminal. Also, at x = 0.125 nm, the rate is 23.9 %, which makes it the lowest along the length of the channel; at x = 1 nm, the rate is 1.4 % lesser than that of the drain terminal. A 1.4 A/mm2 high current density had been achieved in the channel of the device, which is significantly larger than comparable transistors.

Conclusion: The findings of this study reveal that the proposed cylindrical structures transistor, compared to the conventional transistor, not only occupies a smaller area but also demonstrates enhanced efficiency in RF applications. These results suggest the potential for patentable innovations in the field of transistor design and fabrication, offering opportunities for intellectual property development and commercialization.

Graphical Abstract

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