Abstract

Achieve high throughput 128 bits FPGA based Advanced Encryption Standard.

Background: Field Programmable Gate Array (FPGA) provides an efficient platform for design an AES cryptography system. It provides the capability to control each bit using HDL programming language such as VHDL and Verilog which results from an output speed in Gbps rang.

Objective: Use Field Programmable Gate Array (FPGA) to design high throughput 128 bits FPGA based Advanced Encryption Standard.

Method: Pipelining technique has been used to achieve the maximum possible speed. The level of pipelining includes round pipelining and internal component pipelining where a number of registers are inserted in particular places to increase the output speed. The proposed design uses combinatorial logic to implement the byte substitution. The s-box was implemented using composed field arithmetic with 7 stages of pipelining to reduce the combinatorial logic level. The presented model has been implemented using VHDL in Xilinx ISETM 14.4 design tool.

Result: The achieved results were 18.55 Gbps at a clock frequency of 144.96 MHz and an area of 1568 Slices in Spartan3 xc3s1000 hardware.

Conclusion: The results show that the proposed design reaches a high throughput with acceptable area usage compared with other designs in the literature.

Keywords: High throughput AES, 7 stages s-box, fully pipeline AES, FPGA, pipelining, VHDL.

Graphical Abstract