Generic placeholder image

Recent Advances in Electrical & Electronic Engineering

Author(s): Tanmay Dubey*, Vijaya Bhadauria and Rishikesh Pandey

DOI: 10.2174/2352096512666191019130214

DownloadDownload PDF Flyer Cite As
Linearity Enhancement Techniques for Operational Transconductance Amplifier: A Survey

Page: [650 - 668] Pages: 19

  • * (Excluding Mailing and Handling)

Abstract

Background: Operational Transconductance Amplifier (OTA) plays an essential role in many analog and mixed-signal applications that encourages the researchers to contribute their work to design suitable structures of OTA for their applications with acceptable performance parameters.

Methods: The linearity of an OTA is one of its key performance parameters, which affects the performance of the overall system whereas the transconductance value of OTA (Gm) contributes to decide its application area. Low transconductance OTA finds its application in biomedical and neural networks while OTA with higher transconductance is suitable for wireless communication. In any system, it is desirable to obtain a linear voltage-to-current conversion, i.e., OTA, hence various linearization techniques have been reported to linearize the OTA.

Results: In the last two decades, various OTA structures have been reported with linear voltage-tocurrent conversion. Some researchers used attenuation by means of different circuit approaches to linearize the OTA or some used cancellation of nonlinearity terms by using different circuit implementation techniques. Researchers used some other methods also to linearize the OTA viz source degeneration, square root technique and mobility compensation.

Conclusion: The purpose of this paper is to provide a brief survey of various popular linearization techniques reported in the past.

Keywords: Bulk driven, cross coupled differential pair, floating gate, linearity, Operational Transconductance Amplifier, source degeneration.

Graphical Abstract

[1]
E. Sanchez-Sinencio, and J. Silva-Martinez, "CMOS transconductance amplifiers, architectures and active filters: a tutorial", Circuits, Devices Syst. IEEE Proc, , vol. 147, 2000no. 1, pp. 3-12
[http://dx.doi.org/10.1049/ip-cds:20000055]
[2]
R. Chawla, F. Adil, G. Serrano, and P.E. Hasler, "Programmable Gm-C filters using floating-gate op-erational transconductance amplifiers", IEEE Trans. Circuits Syst. I Regul. Pap., vol. 54, no. 3, pp. 481-491, 2007.
[http://dx.doi.org/10.1109/TCSI.2006.887473]
[3]
V.S. Babu, A. Sekhar, R. Salini Devi, and M.R. Baiju, "Floating gate MOSFET based operational transconductance amplifier and study of mismatch", 4th IEEE Conf. Ind. Electron. Appl. ICIEA 2009, 2009pp. 127-132
[4]
J.M. Algueta Miguel, A.J. Lopez-Martin, J. Ramirez-Angulo, and R.G. Carvajal, "Tunable rail-to-rail FGMOS transconductor", ISCAS 2010 - 2010 IEEE Int. Symp. Circuits Syst. Nano-Bio Circuit Fabr. Syst., 2010, pp. 225-228
[5]
J.M.A. Miguel, A.J. Lopez-Martin, L. Acosta, J. Ramirez-Angulo, and R.G. Carvajal, "Using floating gate and quasi-floating gate techniques for rail-to-rail tunable CMOS transconductor design", IEEE Trans. Circuits Syst. I Regul. Pap., vol. 58, no. 7, pp. 1604-1614, 2011.
[http://dx.doi.org/10.1109/TCSI.2011.2157782]
[6]
F. Munoz, A. Torralba, R.G. Carvajal, and J. Tombs, "Floating-Gate-Based Tunable CMOS Low-Voltage Linear Transconductor and Its Application to HF Gm-C Filter Design", IEEE Trans. CIRCUITS Syst. Analog Digit. SIGNAL Process., vol. 48, no. 1, pp. 106-110, 2001.
[http://dx.doi.org/10.1109/82.913194]
[7]
T. Sánchez-Rodríguez, F. Muñoz, J. Galán, R. López-Ahumada, and R.G. Carvajal, "Low voltage linear tunable transconductor for high speed filters", Analog Integr. Circuits Signal Process., vol. 82, no. 1, pp. 329-333, 2015.
[http://dx.doi.org/10.1007/s10470-014-0435-5]
[8]
F. Khateb, "Bulk-driven floating-gate and bulk-driven quasi-floating-gate techniques for low-voltage low-power analog circuits design", AEU Int. J. Electron. Commun., vol. 68, no. 1, pp. 64-72, 2014.
[http://dx.doi.org/10.1016/j.aeue.2013.08.019]
[9]
A. El Mourabit, M.H. Sbaa, Z. Alaoui-Ismaili, and F. Lahjomri, "A CMOS transconductor with high linear range", Proceedings of the IEEE In-ternational Conference on Electronics, Circuits, and Systems, 2007pp. 1131-1134
[http://dx.doi.org/10.1109/ICECS.2007.4511194]
[10]
J.M. Algueta Miguel, C.A. De La Cruz Blas, and A.J. López-Martín, "CMOS triode transconduc-tor based on quasi-floating-gate transistors", Electron. Lett., vol. 46, no. 17, p. 1190, 2010.
[http://dx.doi.org/10.1049/el.2010.1975]
[11]
J.R.E. Hizon, and E. Rodriguez-Villegas, A high transconductance efficiency FGMOS OTA for gm-C ladder filters., Midwest Symp. Circuits Syst, 2012, pp. 105-108.
[12]
A. Veeravalli, S. Member, and S. Member, "Transconductance Amplifier Structures With Very Small Transconductances: A Comparative Design Approach", IEEE J. Solid-State Circuits, vol. 37, no. 6, pp. 770-775, 2002.
[http://dx.doi.org/10.1109/JSSC.2002.1004582]
[13]
F. Khateb, N. Khatib, and D. Kubánek, "Novel ultra-low-power class AB CCII+ Based on floating-gate folded cascode OTA", Circuits Syst. Signal Process., vol. 31, no. 2, pp. 447-464, 2012.
[http://dx.doi.org/10.1007/s00034-011-9340-7]
[14]
J.M.A. Miguel, A.J.L. Martín, J.R. Angulo, and R.G. Carvajal, A Tunable Floating-Gate CMOS Transconductor Based on Current Multiplication., DCIS, pp. 4-7. 2009
[15]
Z. Alsibai, "Floating-Gate Operational Trans-conductance Amplifier", Int. J. Inf. Electron. Eng., vol. 3, no. 4, pp. 361-364, 2013.
[16]
R. Pandey, and M. Gupta, "Low-voltage FGMOS based voltage-to-current converter", Inf. MIDEM, vol. 43, no. 3, pp. 173-178, 2013.
[17]
A.S. Medina-Vazquez, J. De La Cruz-Alejo, F. Gomez-Castaneda, and J.A. Moreno-Cadenas, "Low-voltage linear transconductor and a memory current using the MIFGMOS Transistor", Int. J. Electron., vol. 96, no. 9, pp. 895-914, 2009.
[http://dx.doi.org/10.1080/00207210902941687]
[18]
Y. Berg, "Ultra low-voltage CMOS transcon-ductance amplifiers", Analog Integr. Circuits Signal Process., no. July, pp. 1-10, 2012.
[19]
T. Dubey, and R. Pandey, "Low-Voltage Highly Linear Floating Gate MOSFET Based Source De-generated OTA and its Applications", Inf. MIDEM, vol. 48, no. 1, pp. 19-28, 2018.
[20]
A. El Mourabit, G. Lu, and P. Pittet, "Wide-Linear-Range Subthreshold OTA for Low-Power, Low-Voltage, and Low-Frequency Applications", IEEE Trans. CIRCUITS Syst. Regul. Pap., vol. 52, no. 8, pp. 1481-1488, 2005.
[http://dx.doi.org/10.1109/TCSI.2005.852011]
[21]
E. Farshidi, "A low-voltage class-AB linear transconductance based on floating-gate MOS tech-nology", ECCTD 2009 - European Conference on Circuit Theory and Design Conference Program, 2009, 2009pp. 437-440
[22]
F. Rezaei, and S.J. Azhari, "Ultra Low-voltage, Rail-to-Rail Input/output Stage Operational Trans-conductance Amplifier (OTA) With High Linearity and Its Application in a Gm-C Filter", 11th Int’l Symp. Qual. Electron. Des 2010
[23]
A. Suadet, T. Thongleam, and V. Kasemsuwan, "Quasi-Floating-Gate (QFG) Inverter-Based Class-AB Linear Transconductor for Low Voltage Appli-cations", Int. Conf. Circuits, Syst. Simul. IPCSIT, , vol. 7, , 2011pp. 112-116
[24]
T. Dubey, and V. Bhadauria, "A low-voltage highly linear OTA using bulk-driven floating gate MOSFETs", AEU Int. J. Electron. Commun., vol. 98, pp. 29-37, 2019.
[http://dx.doi.org/10.1016/j.aeue.2018.10.034]
[25]
E.D.C. Cotrim, Analog Integr. Circuits Signal Process., vol. 71, no. 2, pp. 275-282, 2012.
[http://dx.doi.org/10.1007/s10470-011-9618-5]
[26]
A. Yodtean, and A. Thanachayanont, "Sub 1-V highly-linear low-power class-AB bulk-driven tuna-ble CMOS transconductor", Analog Integr. Circuits Signal Process., vol. 75, no. 3, pp. 383-397, 2013.
[http://dx.doi.org/10.1007/s10470-013-0044-8]
[27]
G.D. Colletta, L.H.C. Ferreira, and T.C. Pi-menta, "A 0.25-V 22-nS symmetrical bulk-driven OTA for low-frequency Gm-C applications in 130-nm digital CMOS process", Analog Integr. Circuits Signal Process., vol. 81, no. 2, pp. 377-383, 2014.
[http://dx.doi.org/10.1007/s10470-014-0385-y]
[28]
O. Abdelfattah, G.W. Roberts, I. Shih, and Y.C. Shih, "An ultra-low-voltage CMOS process-insensitive self-biased OTA with rail-to-rail input range", IEEE Trans. Circuits Syst. I Regul. Pap., vol. 62, no. 10, pp. 2380-2390, 2015.
[http://dx.doi.org/10.1109/TCSI.2015.2469011]
[29]
T. Kulej, and F. Khateb, "Bulk-driven adaptive-ly biased OTA in 0.18 μm CMOS", Electron. Lett., vol. 51, no. 6, pp. 458-460, 2015.
[http://dx.doi.org/10.1049/el.2014.4437]
[30]
T. Sharan, and V. Bhadauria, "Sub-threshold, cascode compensated, bulk-driven OTAs with en-hanced gain and phase-margin", Microelectronics J., vol. 54, pp. 150-165, 2016.
[http://dx.doi.org/10.1016/j.mejo.2016.05.009]
[31]
T. Sharan, and V. Bhadauria, "Fully Differen-tial, Bulk-Driven, Class AB, Sub-Threshold OTA With Enhanced Slew Rates and Gain", J. Circuits Syst. Comput., , vol. 26,, no. 01, . 2017.1750001
[http://dx.doi.org/10.1142/S0218126617500013]
[32]
L. Zhang, X. Zhang, and E. El-Masry, "A high-ly linear bulk-driven CMOS OTA for continuous-time filters", Analog Integr. Circuits Signal Process., vol. 54, no. 3, pp. 229-236, 2008.
[http://dx.doi.org/10.1007/s10470-007-9120-2]
[33]
F. Khateb, T. Kulej, and S. Vlassis, "Extremely Low-Voltage Bulk-Driven Tunable Transconduc-tor", Circuits Syst. Signal Process., vol. 36, no. 2, pp. 511-524, 2017.
[http://dx.doi.org/10.1007/s00034-016-0329-0]
[34]
X. Zhang, and E.I. El-Masry, "A novel CMOS OTA based on body-driven MOSFETs and its appli-cations in OTA-C filters", IEEE Trans. Circuits Syst. I Regul. Pap., vol. 54, no. 6, pp. 1204-1212, 2007.
[http://dx.doi.org/10.1109/TCSI.2007.897765]
[35]
A. Yodtean, "0.8-μW CMOS Bulk-Driven Lin-ear Operational Transconductance Amplifier in 0.35-μm Technology", Circuits Syst. (APCCAS), 2010 IEEE Asia Pacific Conf. 2010no. 3, pp. , 784-787
[36]
T. Ohbuchi, and F. Matsumoto, "A design of a low-transconductance linear transconductor utilizing body effect for low frequency applications", ISPACS 2013 - 2013 International Symposium on Intelligent Signal Processing and Communication Systems, 2013, 2013pp., 674-679
[http://dx.doi.org/10.1109/ISPACS.2013.6704634]
[37]
T. Sharan, and V. Bhadauria, "Ultra low-power rail-to-rail linear sub-threshold bulk-driven trans-conductor", 2014 International Conference on Power, Control and Embedded Systems, ICPCES 2014, 2014
[http://dx.doi.org/10.1109/ICPCES.2014.7062826]
[38]
K. Bhange, P. Zode, and P. Zode, "Design of bulk driven miller Operational Transconductance Amplifier", 2015, International Conference on Industrial Instrumentation and Control, ICIC 2015, 2015pp. 1567-1570
[http://dx.doi.org/10.1109/IIC.2015.7150999]
[39]
K. Garradhi, N. Hassen, T. Ettaghzouti, and K. Besbes, "Low voltage low power highly linear OTA using bulk driven technique", Proceedings of the International Conference on Mi-croelectronics, ICM, 2016 no. 1, , pp. 234-237
[40]
S. Abbasalizadeh, Int. J. Circuit Theory Appl., vol. 38, no. 7, pp. 689-708, 2014.
[41]
J.M. Carrillo, J.F. Duque-carrillo, and G. To-relli, "1-V Continuously Tunable CMOS Bulk-Driven Transconductor for Gm-C Filters", IEEE Int. Symp., 2008pp. 896-899
[42]
S. Abbasalizadeh, S. Sheikhaei, and B. Forouzandeh, "A 0.9V Supply OTA in 0.18μm CMOS Technology and Its Application in Realizing a Tunable Low-Pass Gm-C Filter for Wireless Sen-sor Networks", Sci. Res. Circuits Syst., vol. 2013, no. January, pp. 34-43, 2013.
[http://dx.doi.org/10.4236/cs.2013.41007]
[43]
K. Yaohui, Y. Hong, J. Ming, X. Shuzheng, and Y. Huazhong, "Low-Voltage Transconductor with Wide Input Range and Large Tuning Capabil-ity", Tsinghua Sci. Technol., vol. 16, no. 1, pp. 106-112, 2011.
[http://dx.doi.org/10.1016/S1007-0214(11)70017-7]
[44]
E. Cabrera-Bernal, S. Pennisi, A.D. Grasso, A. Torralba, and R.G. Carvajal, "0.7-V Three-Stage Class-AB CMOS Operational Transconductance Amplifier", IEEE Trans. Circuits Syst. I Regul. Pap. 2016 , no. 99, pp. 1807-1815, .
[http://dx.doi.org/10.1109/TCSI.2016.2597440]
[45]
M. Akbari, and O. Hashemipour, "A 0.6-V, 0.4-μW bulk-driven operational amplifier with rail-to-rail input/output swing", Analog Integr. Circuits Signal Process., vol. 86, no. 2, pp. 341-351, 2016.
[http://dx.doi.org/10.1007/s10470-015-0686-9]
[46]
M. Akbari, and O. Hashemipour, "A 63-dB gain OTA operating in subthreshold with 20-nW power consumption", Int. J. Circuit Theory Appl., vol. 45, no. 6, pp. 843-850, 2017.
[http://dx.doi.org/10.1002/cta.2248]
[47]
T. Sharan, P. Chetri, and V. Bhadauria, "Ultra-low-power bulk-driven fully differential subthreshold OTAs with partial positive feedback for Gm -C filters", Analog Integr. Circuits Signal Process., vol. 94, no. 3, pp. 427-447, 2018.
[http://dx.doi.org/10.1007/s10470-017-1065-5]
[48]
U. Sharma, T. Dubey, and V. Bhadauria, "Lin-earity Enhancement using Bulk-Degeneration for Source Degenerated OTAs", 2018 Second Inter-national Conference on Advances in Electronics, Computers and Communications (ICAECC), 2018pp. 1-5
[49]
T. Kulshreshtha, and V. Bhadauria, "A highly linear cmos pseudo differential transconductor us-ing active attenuator", ICPCES 2010 - Int. Conf. Power, Control Embed. Syst., 2010pp. 2-5
[50]
V. Bhadauria, K. Kant, and S. Banerjee, "Line-arity Enhancement of 0.18 μm Transconductor us-ing Active Attenuation Technique", Can. J. Electr. Electron. Eng., vol. 2, no. 12, pp. 598-601, 2011.
[51]
C.F.T. Soares, G.S. de Moraes, and A. Pet-raglia, "A low-transconductance OTA with im-proved linearity suitable for low-frequency Gm-C filters", Microelectronics J., vol. 45, no. 11, pp. 1499-1507, 2014.
[http://dx.doi.org/10.1016/j.mejo.2014.07.008]
[52]
S.J. Hsu, C.Y. Lu, and C.C. Hung, "40MHz Gm-C filter with high linearity OTA for wireless applications", Int. Symp. VLSI Des. Autom. Test, VLSI-DAT 2012 - Proc. Tech. Pap., 2012pp. 0-3
[53]
S.K. Kar, and S. Sen, "A highly linear CMOS transconductance amplifier in 180 nm process tech-nology", Analog Integr. Circuits Signal Process., vol. 72, no. 1, pp. 163-171, 2012.
[http://dx.doi.org/10.1007/s10470-011-9796-1]
[54]
C. Sawigun, D. Pal, and A. Demosthenous, "A wide-input linear range sub-threshold transconduc-tor for sub-Hz filtering", ISCAS 2010 - 2010 IEEE Int. Symp. Circuits Syst. Nano-Bio Circuit Fabr. Syst., vol. vol. 1,, 2010pp. 1567-1570
[55]
S.K. Kar, and S. Sen, "Linearity improvement of source degenerated transconductance amplifi-ers", Analog Integr. Circuits Signal Process., vol. 74, no. 2, pp. 399-407, 2013.
[http://dx.doi.org/10.1007/s10470-012-9948-y]
[56]
V. Bhadauria, and K. Kant, "A novel technique for tuning low voltage linear transconductor", International Conference on Electronic Devices, Systems and Applications, ICEDSA 2010 - Proceed- ings, 2010pp. 22-25
[http://dx.doi.org/10.1109/ICEDSA.2010.5503108]
[57]
V. Bhadauria, K. Kant, and S. Banerjee, "A tunable transconductor with high linearity", Proceedings, APCCAS, 2010pp. 5-8
[58]
V. Bhadauria, K. Kant, and S. Banerjee, "De-sign and Analysis of a Power Efficient Linearly Tunable Cross-Coupled Transconductor Having Separate Bias Control", Circuits Syst., vol. 1, no. January, pp. 99-106, 2012.
[http://dx.doi.org/10.4236/cs.2012.31013]
[59]
A. Lewinski, and J. Silva-Martinez, "OTA Line-arity Enhancement Technique for High Frequency Applications With IM3 Below -65 dB", IEEE Trans. Circuits Syst., II Express Briefs, vol. 51, no. 10, pp. 542-548, 2004.
[http://dx.doi.org/10.1109/TCSII.2004.834531]
[60]
A. Lewinski, and J. Silva-Martinez, "A High-Frequency Transconductor Using a Robust Nonline-arity Cancellation", IEEE Trans. Circuits Syst., II Express Briefs, vol. 53, no. 9, pp. 896-900, 2006.
[http://dx.doi.org/10.1109/TCSII.2006.880025]
[61]
I.S. Han, "A Novel Tunable Transconductance Amplifier Based on Voltage-Controlled Resistance by MOS Transistors", IEEE Trans. Circuits Syst., II Express Briefs, vol. 53, no. 8, pp. 662-666, 2006.
[http://dx.doi.org/10.1109/TCSII.2006.875309]
[62]
D-L. Shen, Y-J. Chu, and H-W. Chen, "A linearized technique in an All-MOS transconduct-ance amplifier", Microelectronics J., vol. 43, no. 12, pp. 1023-1028, 2012.
[http://dx.doi.org/10.1016/j.mejo.2012.07.017]
[63]
J. Wang, C. Li, L. Ye, H. Liao, and R. Huang, "Highly linear OTA with 3rd-order nonlinearity su-perposition techniques for Gm-C low-pass filter with 34dBm IIP3", IEEE 11th Int. Conf. Solid-State Integr. Circuit Technol, 2012pp. 1-3
[64]
K.C. Kuo, and A. Leuciuc, "A linear MOS transconductor using source degeneration and adap-tive biasing", IEEE Trans. Circuits Syst. II Analog Digit. Signal Process., vol. 48, no. 10, pp. 937-943, 2001.
[http://dx.doi.org/10.1109/82.974782]
[65]
S. Ouzounov, E. Roza, J.A.H. Hegt, G. Van Der Weide, and A.H.M. Van Roermund, "A CMOS V – I Converter With 75-dB SFDR and 360- W Power Consumption", IEEE J. Solid-State Circuits, vol. 40, no. 7, pp. 1527-1532, 2005.
[http://dx.doi.org/10.1109/JSSC.2005.847496]
[66]
A. Sarrafinazhad, I. Kara, and F. Baskaya, "Design of a digitally tunable 5th order Gm-C filter using linearized OTA in 90nm CMOS technology", ISSCS 2015 - International Symposium on Signals, Circuits and Systems, vol. 2, 2015, pp. 2-5
[67]
P. Khumsat, "Linearisation technique for low-voltage tuneable Nauta’s transconductor in Gm − C filter design", IET Circuits Dev. Syst., vol. 12, no. 4, pp. 347-361, 2018.
[http://dx.doi.org/10.1049/iet-cds.2017.0177]
[68]
A.M. Ismail, and A.M. Soliman, "“Novel CMOS wide-linear-range transconductance amplifi-er,” IEEE Trans. Circuits Syst. I Fundam", Theory Appl., vol. 47, no. 8, pp. 1248-1253, 2000.
[69]
H. Le-Thai, H-H. Nguyen, H-N. Nguyen, H-S. Cho, J-S. Lee, and S-G. Lee, "An IF Bandpass Filter Based on a Low Distortion Transconductor", IEEE J. Solid-State Circuits, vol. 45, no. 11, pp. 2250-2261, 2010.
[http://dx.doi.org/10.1109/JSSC.2010.2063991]
[70]
M. Abdulaziz, W. Ahmad, M. Tormanen, and H. Sjoland, "A Linearization Technique for Differ-ential OTAs", IEEE Trans. Circuits Syst., II Express Briefs, vol. 64, no. 9, pp. 1002-1006, 2017.
[http://dx.doi.org/10.1109/TCSII.2016.2617920]
[71]
S. Ouzounov, E. Roza, and H. Hegt, "G. v d Weide, and A. van Roermund, “Design of MOS transcon-ductors with low noise and low harmonic distortion for minimum current consumption", Integr. VLSI J., vol. 40, no. 3, pp. 365-379, 2007.
[http://dx.doi.org/10.1016/j.vlsi.2006.03.001]
[72]
T. Nguyen, and S. Lee, "Low-voltage, low-power CMOS operation transconductance amplifier with rail-to-rail differential input range", 2006 IEEE Int. Symp. Circuits Syst, 2006p. 4
[http://dx.doi.org/10.1109/ISCAS.2006.1692916]
[73]
P. Monsurrò, S. Pennisi, G. Scotti, and A. Trifi-letti, "Linearization technique for source-degenerated CMOS differential transconductors", IEEE Trans. Circuits Syst., II Express Briefs, vol. 54, no. 10, pp. 848-852, 2007.
[http://dx.doi.org/10.1109/TCSII.2007.906203]
[74]
J. Gak, M.R. Miguez, and A. Arnaud, "Na-nopower OTAs with improved linearity and low in-put offset using bulk degeneration", IEEE Trans. Circuits Syst. I Regul. Pap., vol. 61, no. 3, pp. 689-698, 2014.
[http://dx.doi.org/10.1109/TCSI.2013.2284002]
[75]
X. Cheng, "A novel pseudo differential trans-conductor for IEEE 802.11 WLANs", Analog Integr. Circuits Signal Process., vol. 81, no. 2, pp. 385-391, 2014.
[http://dx.doi.org/10.1007/s10470-014-0409-7]
[76]
T. Ohbuchi, and F. Matsumoto, "A low-power and low-Gm linear transconductor utilizing control of a threshold voltage", Analog Integr. Circuits Signal Process., vol. 85, no. 2, pp. 263-273, 2015.
[http://dx.doi.org/10.1007/s10470-015-0618-8]
[77]
K. Garradhi, N. Hassen, T. Ettaghzouti, and K. Besbes, "Highly linear low voltage low power OTA using source-degeneration technique and universal filter application", Proceedings of the International Conference on Mi-croelectronics, ICM, 2016pp. 295-298
[78]
F. Rezaei, "Linearity enhancement in the entire tuning range of CMOS OTA using a new tune com-pensated source degeneration technique", Microelectronics J., vol. 66, no. April, pp. 128-135, 2017.
[http://dx.doi.org/10.1016/j.mejo.2017.06.008]
[79]
M.B. Elamien, and S.A. Mahmoud, "A Linear CMOS Balanced Output Transconductor Using Double Differential Pair with Source Degeneration and Adaptive Biasing", Midwest Symp., 2016
[http://dx.doi.org/10.1109/MWSCAS.2016.7870002]
[80]
B. Calvo, S. Celma, M.T. Sanz, and P.A. Mar-tinez, "A high-linear wide-tunable CMOS transconductor for video frequency applications", Microelectron. Reliab., vol. 44, no. 7, pp. 1189-1198, 2004.
[81]
A.J. López-martín, J. Ramirez-angulo, C. Dur-bha, R.G. Carvajal, S. Member, and A. Abstract, "A CMOS Transconductor with Multidecade Tuning Using Balanced Current Scaling in Moderate Inver-sion", IEEE J. Solid-State Circuits, vol. 40, no. 5, pp. 1078-1083, 2005.
[http://dx.doi.org/10.1109/JSSC.2005.845980]
[82]
M. Kachare, A.J. López-Martín, J. Ramirez-Angulo, and R.G. Carvajal, "A compact tunable CMOS transconductor with high linearity", IEEE Trans. Circuits Syst., II Express Briefs, vol. 52, no. 2, pp. 82-84, 2005.
[http://dx.doi.org/10.1109/TCSII.2004.842065]
[83]
A. Petraglia, "Linearly Tunable CMOS OTA With Constant Dynamic Range Using Source-Degenerated Current Mirrors", IEEE Trans. Circuits Syst., II Express Briefs, vol. 53, no. 9, pp. 797-801, 2006.
[http://dx.doi.org/10.1109/TCSII.2006.881162]
[84]
K. Yaohui, and Y. Huazhong, "“A novel trans-conductor with high linearity,” in ISSCS 2007 - In-ternational Symposium on Signals, Circuits and Systems", Proceedings, vol. 1, pp. 61-64, 2007.
[85]
M. Jiménez-Fuentes, R.G. Carvajal, L. Acosta, C. Rubia-Marcos, A. López-Martín, and J. Ramirez-Angulo, "A tunable highly linear CMOS transcon-ductor with 80 dB of SFDR", Integr. VLSI J., vol. 42, no. 3, pp. 277-285, 2009.
[http://dx.doi.org/10.1016/j.vlsi.2008.11.002]
[86]
J.M. Martinez-heredia, and A. Torralba, "En-hanced source-degenerated CMOS differential transconductor", Microelectronics J., vol. 42, no. 2, pp. 396-402, 2011.
[http://dx.doi.org/10.1016/j.mejo.2010.10.011]
[87]
M.B. Elamien, and S.A. Mahmoud, "Analysis and design of a highly linear CMOS OTA for porta-ble biomedical applications in 90 nm CMOS", Microelectronics J., vol. 70, no. June, pp. 72-80, 2017.
[http://dx.doi.org/10.1016/j.mejo.2017.10.009]
[88]
M.B. Elamien, and S.A. Mahmoud, "On the design of highly linear CMOS digitally programma-ble operational transconductance amplifiers for low and high-frequency applications., vol. Vol. 2", Analog Integr. Circuits Signal Process., 2018.
[89]
J. Mahattanakul, and C. Toumazou, "Independ-ent control of transconductance gain and input line-ar range in a MOS linear transconductance amplifi-er", Electron. Lett., vol. 32, no. 18, pp. 1629-1630, 1996.
[http://dx.doi.org/10.1049/el:19961107]
[90]
C. Sawigun, and J. Mahattanakul, "A Compact High Current Efficiency Low-Voltage MOS Trans-conductor with Nearly Constant Input Voltage Range", 2007, IEEE Int. Symp. Circuits Syst, 2007pp. 221-224
[http://dx.doi.org/10.1109/ISCAS.2007.378316]
[91]
W. Ngamkham, N. Kiatwarin, W. Narksap, W. Sangpisit, and W. Kiranon, "A linearized source-couple pair transconductor using a low-voltage square root circuit", 5th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology, ECTI-CON 2008 , vol. 2, , 2008pp. 701-704
[http://dx.doi.org/10.1109/ECTICON.2008.4600527]
[92]
A.L. Coban, and P.E. Allen, "Low-voltage CMOS transconductance cell based on parallel op-eration of triode and saturation transconductors", Electron. Lett., vol. 30, no. 14, pp. 1124-1126, 1994.
[http://dx.doi.org/10.1049/el:19940756]
[93]
S.H. Yang, K.H. Kim, Y.H. Kim, Y. You, and K.R. Cho, "A novel CMOS operational trans-conductance amplifier based on a mobility compen-sation technique", IEEE Trans. Circuits Syst., II Express Briefs, vol. 52, no. 1, pp. 37-42, 2005.
[http://dx.doi.org/10.1109/TCSII.2004.839539]
[94]
T.Y. Lo, and C.C. Hung, "A 1-V 50-MHz pseudo differential OTA with compensation of the mobility reduction", IEEE Trans. Circuits Syst., II Express Briefs, vol. 54, no. 12, pp. 1047-1051, 2007.
[http://dx.doi.org/10.1109/TCSII.2007.907559]
[95]
P. Tongpoon, T. Miyazawa, F. Matsumoto, S. Nakamura, and Y. Noguchi, "Design of a linear transconductor considering effects of weak inver-sion region and mobility degradation", ISPACS 2009 - 2009 Int. Symp. Intell. Signal Pro-cess. Commun. Syst. Proc., no. Ispacs, 2009pp. 280-283
[96]
T-Y. Lo, C-C. Hung, and C-H. Lo, "Linear low voltage nano-scale CMOS transconductor", Analog Integr. Circuits Signal Process., vol. 66, no. 1, pp. 1-7, 2011.
[http://dx.doi.org/10.1007/s10470-010-9520-6]
[97]
T.Y. Lo, and C.C. Hung, "1-V linear CMOS transconductor with-65 dB THD in nano-scale CMOS technology", 2007 Ieee International Symposium on Circuits and Systems, , vol. Vols 1-11, vol. 1,, 2007pp. 3792-3795
[http://dx.doi.org/10.1109/ISCAS.2007.378787]
[98]
T. Farouk, A. Nader Mohieldin, and A. Hussien Khalil, "A low-voltage low-power CMOS fully dif-ferential linear transconductor with mobility reduc-tion compensation", Microelectronics J., vol. 43, no. 1, pp. 69-76, 2012.
[http://dx.doi.org/10.1016/j.mejo.2011.11.001]
[99]
P. Tongpoon, F. Matsumoto, H. Takeuchi, T. Ohbuchi, and R. Ishio, "A novel design of local-feedback MOS transconductor using techniques for cancellation of mobility degradation and lineariza-tion of differential output current characteristic", Analog Integr. Circuits Signal Process., vol. 72, no. 3, pp. 565-574, 2012.
[http://dx.doi.org/10.1007/s10470-011-9783-6]
[100]
D.V. Morozov, and A.S. Korotkov, "“A reali-zation of low-distortion CMOS transconductance amplifier,” IEEE Trans. Circuits Syst. I Fundam", Theory Appl., vol. 48, no. 9, pp. 1138-1141, 2001.
[101]
W. Jendernalik, S. Szczepanski, and S. Koziel, "Highly linear CMOS triode transconductor for VHF applications", IET Circuits Dev. Syst., vol. 6, no. 1, p. 9, 2012.
[http://dx.doi.org/10.1049/iet-cds.2011.0138]
[102]
T.Y. Lo, and C.C. Hung, "A High Speed Pseudo-Differential OTA with Mobility Compensa-tion Technique in 1-V Power Supply Voltage", 2006, IEEE Asian Solid-State Circuits Conf., 2006pp. 163-166
[http://dx.doi.org/10.1109/ASSCC.2006.357876]
[103]
E. Rodriguez-Villegas, Low Power and Low Voltage Circuit Design with the FGMOS Transistor., IET, 2006.
[http://dx.doi.org/10.1049/PBCS020E]
[104]
F. Masuoka, R. Shirota, and K. Sakui, "Re-views and Prospects of Non-Volatile Semiconductor Memories", IEICE Trans. Electron., vol. 74, no. 4, pp. 868-874, 1991.
[105]
B. Nauta, "A CMOS Transconductance-C Fil-ter Technique for Very High Frequencies", IEEE J. Solid-State Circuits, vol. 27, no. 2, pp. 142-153, 1992.
[http://dx.doi.org/10.1109/4.127337]
[106]
J. Kim, and R.L. Geiger, "Performance Char-acterization of an Active Attenuator Using Two Cascaded MOSFETs", Proc. 36th Midwest Symp. Circuits Syst, 1993pp. 716-720
[107]
J.Y. Kim, and R.L. Geiger, "Characterisation of linear MOS active attenuator and amplifier", Electron. Lett., vol. 31, no. 7, pp. 4-6, 1994.
[108]
J.M. Carrillo, G. Torelli, and J.F. Duque-Carrillo, "Transconductance enhancement in bulk-driven input stages and its applications", Analog Integr. Circuits Signal Process., vol. 68, pp. 207-217, 2011.
[http://dx.doi.org/10.1007/s10470-011-9603-z]