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Nanoscience & Nanotechnology-Asia

Author(s): Sanjit K. Swain*, Sudhansu M. Biswal, Satish K. Das, Sarosij Adak and Biswajit Baral

DOI: 10.2174/2210681209666190919094434

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Performance Comparison of InAs Based DG-MOSFET with Respect to SiO2 and Gate Stack Configuration

Page: [419 - 424] Pages: 6

  • * (Excluding Mailing and Handling)

Abstract

Objective: In this proposed work, the Analog, RF and Linearity performances of a DGMOSFET have been analyzed by considering InAs as a channel material.

Methods: For the very first time, gate stack techniques in this device have been incorporated and a comparative analysis is conducted with respect to SiO2 oxide layer. The variations in different patterns of oxide layer and their comparison have been thoroughly investigated to have a better understanding of various performance parameters. A thorough analysis of the key figure-of-merits such as trans-conductance factor, transconductance generation factor (TGF), gate capacitance, cutoff frequency (fT), maximum frequency of oscillation (fmax), GBW and various linearity parameters such as gm2, gm3,VIP2, VIP3, IIP3, has been studied with respect to SiO2 oxide material and gate stack technology.

Result: The simulation results revealed that the performances of the device are sensitive to both the oxide materials and it was also inferred that gate stack technology gave a better performance over SiO2 oxide layer.

Conclusion: These results have significant effects in analog, RF and linearity operations. In this work, computer aided design (TCAD) simulations by 2D ATLAS, Silvaco International have been used.

Keywords: Gate stack, InAs channel, analog applications, RF applications, linearity behavior, ATLAS.

Graphical Abstract

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