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Nanoscience & Nanotechnology-Asia

Author(s): T.P. Dash*, S. Dey, S. Das, J. Jena, E. Mahapatra and C.K. Maiti

DOI: 10.2174/2210681209666190809101307

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Source/Drain Stressor Design for Advanced Devices at 7 nm Technology Node

Page: [447 - 456] Pages: 10

  • * (Excluding Mailing and Handling)

Abstract

Background: In nano and microelectronics, device performance enhancement is limited by downscaling. Introduction of intentional mechanical stress is a potential mobility booster to overcome these limitations. This paper explores the key design challenges of stress-engineered FinFETs based on the epitaxial SiGe S/D at 7 nm Technology node.

Objective: To study the mechanical stress evolution in a tri-gate FinFET at 7 nm technology node using technology CAD (TCAD) simulations. Using stress maps, we analyze the mechanical stress impact on the transfer characteristics of the devices through device simulation.

Methods: 3D sub-band Boltzmann transport analysis for tri-gate PMOS FinFETs was used, with 2D Schrödinger solution in the fin cross-section and 1D Boltzmann transport along the channel.

Results: Using stress maps, the mechanical stress impact on the transfer characteristics of the device through device simulation has been analyzed.

Conclusion: Suitability of predictive TCAD simulations to explore the potential of innovative strain-engineered FinFET structures for future generation CMOS technology is demonstrated.

Keywords: Strain engineering, FinFETs, SiGe, source/drain stressor design, stress tuning, TCAD, ballistic transport, driftdiffusion, quantum transport solver, Subband Boltzmann transport equation solver.

Graphical Abstract

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